(1) Field of the Invention
This invention relates to a semiconductor device and, more particularly, to a semiconductor device having MOS transistors each of which functions as a capacitor.
(2) Description of the Related Art
To decrease noise which appears on power supply lines in semiconductor devices, such as large scale integrated circuits (LSIs), there are cases where a metal oxide semiconductor (MOS) transistor to be used as a capacitor (MOS capacitor) is connected between a power supply terminal and GND as a bypass capacitor.
FIGS. 3A and 3B are circuit diagrams of a conventional semiconductor device using a single MOS capacitor between a power supply terminal and GND. FIG. 3A is a circuit diagram of a conventional semiconductor device using an n-channel MOS transistor as the single MOS capacitor. FIG. 3B is a circuit diagram of a conventional semiconductor device using a p-channel MOS transistor as the single MOS capacitor.
In FIG. 3A, to make an n-channel MOS transistor (NMOS transistor) 50 function as a MOS capacitor, a gate (G) of the NMOS transistor 50 is connected to a power supply terminal VDD and source/drain (S/D) regions of the NMOS transistor 50 are connected to GND.
In FIG. 3B, to make a p-channel MOS transistor (PMOS transistor) 51 function as a MOS capacitor, a gate of the PMOS transistor 51 is connected to GND and source/drain (S/D) regions of the PMOS transistor 51 are connected to a power supply terminal VDD.
However, if a single MOS capacitor is used between power supply and GND, voltage between the power supply and GND is applied between the gate and the source/drain regions of the MOS capacitor. This may cause a dielectric breakdown of a gate oxide in the MOS capacitor. Accordingly, there is a problem with its reliability.
To solve this problem, a circuit in which two MOS capacitors are connected in series is disclosed with the aim of decreasing voltage applied between the gate and the source/drain regions of one MOS capacitor (see, for example, Japanese Unexamined Patent Publication No. Hei10-256489).
FIG. 4 is an example of a circuit diagram of a conventional semiconductor device using two MOS capacitors between a power supply terminal and GND.
In this circuit, two MOS capacitors are connected between a power supply terminal VDD and GND. That is to say, this circuit includes an NMOS transistor 52 a gate of which is connected to the power supply terminal VDD and an NMOS transistor 53 a gate of which is connected to source/drain regions of the NMOS transistor 52 and source/drain regions of which is connected to GND. Substrate portions on which the NMOS transistors 52 and 53 are formed are connected to GND.
With this circuit, the two MOS capacitors are connected between the power supply terminal VDD and GND, so voltage applied between the gate and the source/drain regions of one MOS capacitor can be decreased.